1301 lines
29 KiB
C
1301 lines
29 KiB
C
#ifndef _OV2640_SETTINGS_H_
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#define _OV2640_SETTINGS_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "ov2640_regs.h"
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// 30fps@24MHz
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const DRAM_ATTR uint8_t ov2640_settings_cif[][2] = {
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{BANK_SEL, BANK_SEL_DSP},
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{0x2c, 0xff},
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{0x2e, 0xdf},
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{BANK_SEL, BANK_SEL_SENSOR},
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{0x3c, 0x32},
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{CLKRC, 0x01},
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{COM2, COM2_OUT_DRIVE_3x},
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{REG04, REG04_DEFAULT},
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{COM8, COM8_DEFAULT | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN},
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{COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
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{0x2c, 0x0c},
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{0x33, 0x78},
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{0x3a, 0x33},
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{0x3b, 0xfB},
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{0x3e, 0x00},
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{0x43, 0x11},
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{0x16, 0x10},
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{0x39, 0x92},
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{0x35, 0xda},
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{0x22, 0x1a},
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{0x37, 0xc3},
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{0x23, 0x00},
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{ARCOM2, 0xc0},
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{0x06, 0x88},
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{0x07, 0xc0},
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{COM4, 0x87},
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{0x0e, 0x41},
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{0x4c, 0x00},
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{0x4a, 0x81},
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{0x21, 0x99},
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{AEW, 0x40},
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{AEB, 0x38},
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{VV, VV_AGC_TH_SET(8,2)},
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{0x5c, 0x00},
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{0x63, 0x00},
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{HISTO_LOW, 0x70},
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{HISTO_HIGH, 0x80},
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{0x7c, 0x05},
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{0x20, 0x80},
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{0x28, 0x30},
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{0x6c, 0x00},
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{0x6d, 0x80},
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{0x6e, 0x00},
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{0x70, 0x02},
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{0x71, 0x94},
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{0x73, 0xc1},
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{0x3d, 0x34},
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{0x5a, 0x57},
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{BD50, 0xbb},
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{BD60, 0x9c},
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{COM7, COM7_RES_CIF},
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{HSTART, 0x11},
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{HSTOP, 0x43},
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{VSTART, 0x00},
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{VSTOP, 0x25},
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{REG32, 0x89},
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{0x37, 0xc0},
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{BD50, 0xca},
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{BD60, 0xa8},
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{0x6d, 0x00},
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{0x3d, 0x38},
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{BANK_SEL, BANK_SEL_DSP},
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{0xe5, 0x7f},
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{MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL},
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{0x41, 0x24},
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{RESET, RESET_JPEG | RESET_DVP},
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{0x76, 0xff},
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{0x33, 0xa0},
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{0x42, 0x20},
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{0x43, 0x18},
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{0x4c, 0x00},
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{CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
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{0x88, 0x3f},
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{0xd7, 0x03},
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{0xd9, 0x10},
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{R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x02},
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{0xc8, 0x08},
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{0xc9, 0x80},
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{BPADDR, 0x00},
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{BPDATA, 0x00},
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{BPADDR, 0x03},
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{BPDATA, 0x48},
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{BPDATA, 0x48},
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{BPADDR, 0x08},
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{BPDATA, 0x20},
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{BPDATA, 0x10},
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{BPDATA, 0x0e},
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{0x90, 0x00},
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{0x91, 0x0e},
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{0x91, 0x1a},
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{0x91, 0x31},
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{0x91, 0x5a},
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{0x91, 0x69},
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{0x91, 0x75},
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{0x91, 0x7e},
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{0x91, 0x88},
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{0x91, 0x8f},
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{0x91, 0x96},
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{0x91, 0xa3},
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{0x91, 0xaf},
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{0x91, 0xc4},
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{0x91, 0xd7},
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{0x91, 0xe8},
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{0x91, 0x20},
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{0x92, 0x00},
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{0x93, 0x06},
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{0x93, 0xe3},
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{0x93, 0x05},
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{0x93, 0x05},
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{0x93, 0x00},
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{0x93, 0x04},
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{0x93, 0x00},
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{0x93, 0x00},
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{0x93, 0x00},
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{0x93, 0x00},
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{0x93, 0x00},
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{0x93, 0x00},
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{0x93, 0x00},
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{0x96, 0x00},
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{0x97, 0x08},
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{0x97, 0x19},
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{0x97, 0x02},
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{0x97, 0x0c},
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{0x97, 0x24},
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{0x97, 0x30},
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{0x97, 0x28},
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{0x97, 0x26},
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{0x97, 0x02},
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{0x97, 0x98},
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{0x97, 0x80},
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{0x97, 0x00},
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{0x97, 0x00},
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{0xa4, 0x00},
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{0xa8, 0x00},
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{0xc5, 0x11},
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{0xc6, 0x51},
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{0xbf, 0x80},
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{0xc7, 0x10},
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{0xb6, 0x66},
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{0xb8, 0xA5},
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{0xb7, 0x64},
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{0xb9, 0x7C},
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{0xb3, 0xaf},
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{0xb4, 0x97},
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{0xb5, 0xFF},
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{0xb0, 0xC5},
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{0xb1, 0x94},
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{0xb2, 0x0f},
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{0xc4, 0x5c},
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{CTRL1, 0xfd},
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{0x7f, 0x00},
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{0xe5, 0x1f},
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{0xe1, 0x67},
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{0xdd, 0x7f},
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{IMAGE_MODE, 0x00},
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{RESET, 0x00},
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{R_BYPASS, R_BYPASS_DSP_EN},
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{0, 0}
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};
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const DRAM_ATTR uint8_t ov2640_settings_to_cif[][2] = {
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{BANK_SEL, BANK_SEL_SENSOR},
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{COM7, COM7_RES_CIF},
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{COM1, 0x0A},//?
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{REG32, REG32_CIF},
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{CLKRC, 0x01},
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{HSTART, 0x11},
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{HSTOP, 0x43},
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{VSTART, 0x00},
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{VSTOP, 0x25},
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{BD50, 0xca},
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{BD60, 0xa8},
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{0x5a, 0x23},
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{0x6d, 0x00},
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{0x3d, 0x38},
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{0x39, 0x92},
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{0x35, 0xda},
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{0x22, 0x1a},
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{0x37, 0xc3},
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{0x23, 0x00},
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{ARCOM2, 0xc0},
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{0x06, 0x88},
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{0x07, 0xc0},
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{COM4, 0x87},
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{0x0e, 0x41},
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{0x4c, 0x00},
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{BANK_SEL, BANK_SEL_DSP},
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{RESET, RESET_DVP},
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{HSIZE8, 0x32},
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{VSIZE8, 0x25},
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{SIZEL, 0x00},
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{HSIZE, 0x64},
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{VSIZE, 0x4a},
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{XOFFL, 0x00},
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{YOFFL, 0x00},
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{VHYX, 0x00},
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{TEST, 0x00},
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{CTRL2, CTRL2_DCW_EN | 0x1D},
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{CTRLI, CTRLI_LP_DP | 0x00},
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{R_DVP_SP, 0x82},
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{0, 0}
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};
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const DRAM_ATTR uint8_t ov2640_settings_to_svga[][2] = {
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{BANK_SEL, BANK_SEL_SENSOR},
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{COM7, COM7_RES_SVGA},
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{COM1, 0x0A},
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{REG32, REG32_SVGA},
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{CLKRC, 0x01},
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{HSTART, 0x11},
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{HSTOP, 0x43},
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{VSTART, 0x00},
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{VSTOP, 0x4b},
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{0x37, 0xc0},
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{BD50, 0xca},
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{BD60, 0xa8},
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{0x5a, 0x23},
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{0x6d, 0x00},
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{0x3d, 0x38},
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{0x39, 0x92},
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{0x35, 0xda},
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{0x22, 0x1a},
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{0x37, 0xc3},
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{0x23, 0x00},
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{ARCOM2, 0xc0},
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{0x06, 0x88},
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{0x07, 0xc0},
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{COM4, 0x87},
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{0x0e, 0x41},
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{0x42, 0x03},
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{0x4c, 0x00},
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{BANK_SEL, BANK_SEL_DSP},
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{RESET, RESET_DVP},
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{HSIZE8, 0x64},
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{VSIZE8, 0x4B},
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{SIZEL, 0x00},
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{HSIZE, 0xC8},
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{VSIZE, 0x96},
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{XOFFL, 0x00},
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{YOFFL, 0x00},
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{VHYX, 0x00},
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{TEST, 0x00},
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{CTRL2, CTRL2_DCW_EN | 0x1D},
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{CTRLI, CTRLI_LP_DP | 0x00},
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{R_DVP_SP, 0x80},
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{0, 0}
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};
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const DRAM_ATTR uint8_t ov2640_settings_to_uxga[][2] = {
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{BANK_SEL, BANK_SEL_SENSOR},
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{COM7, COM7_RES_UXGA},
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{COM1, 0x0F},
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{REG32, REG32_UXGA},
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{CLKRC, 0x01},
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{HSTART, 0x11},
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{HSTOP, 0x75},
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{VSTART, 0x01},
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{VSTOP, 0x97},
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{0x3d, 0x34},
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{BD50, 0xbb},
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{BD60, 0x9c},
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{0x5a, 0x57},
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{0x6d, 0x80},
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{0x39, 0x82},
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{0x23, 0x00},
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{0x07, 0xc0},
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{0x4c, 0x00},
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{0x35, 0x88},
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{0x22, 0x0a},
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{0x37, 0x40},
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{ARCOM2, 0xa0},
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{0x06, 0x02},
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{COM4, 0xb7},
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{0x0e, 0x01},
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{0x42, 0x83},
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{BANK_SEL, BANK_SEL_DSP},
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{RESET, RESET_DVP},
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{HSIZE8, 0xc8},
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{VSIZE8, 0x96},
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{SIZEL, 0x00},
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{HSIZE, 0x90},
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{VSIZE, 0x2c},
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{XOFFL, 0x00},
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{YOFFL, 0x00},
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{VHYX, 0x88},
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{TEST, 0x00},
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{CTRL2, CTRL2_DCW_EN | 0x1d},
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{CTRLI, 0x00},
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{R_DVP_SP, 0x82},
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{0, 0}
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};
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const DRAM_ATTR uint8_t ov2640_settings_jpeg3[][2] = {
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{BANK_SEL, BANK_SEL_DSP},
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{RESET, RESET_JPEG | RESET_DVP},
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{0xE1, 0x77},
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{0xE5, 0x1F},
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{0xD7, 0x03},
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{0xd9, 0x10},
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{IMAGE_MODE, IMAGE_MODE_JPEG_EN | IMAGE_MODE_HREF_VSYNC},
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{0xdf, 0x80},
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{0x33, 0x80},
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{0x3c, 0x10},
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{R_DVP_SP, 0x04},
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{0xeb, 0x30},
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{0xdd, 0x7f},
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{RESET, 0x00},
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{0, 0}
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};
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static const uint8_t ov2640_settings_yuv422[][2] = {
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{BANK_SEL, BANK_SEL_DSP},
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{RESET, RESET_DVP},
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{IMAGE_MODE, IMAGE_MODE_YUV422},
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{0xD7, 0x01},
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{0xE1, 0x67},
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{RESET, 0x00},
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{0, 0},
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};
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static const uint8_t ov2640_settings_rgb565[][2] = {
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{BANK_SEL, BANK_SEL_DSP},
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{RESET, RESET_DVP},
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{IMAGE_MODE, IMAGE_MODE_RGB565},
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{0xD7, 0x03},
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{0xE1, 0x77},
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{RESET, 0x00},
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{0, 0},
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};
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#define NUM_BRIGHTNESS_LEVELS (5)
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static const uint8_t brightness_regs[NUM_BRIGHTNESS_LEVELS + 1][5] = {
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{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
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{0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
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{0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
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{0x00, 0x04, 0x09, 0x20, 0x00 }, /* 0 */
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{0x00, 0x04, 0x09, 0x30, 0x00 }, /* +1 */
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{0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
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};
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#define NUM_CONTRAST_LEVELS (5)
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static const uint8_t contrast_regs[NUM_CONTRAST_LEVELS + 1][7] = {
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{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA, BPDATA, BPDATA },
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{0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
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{0x00, 0x04, 0x07, 0x20, 0x1c, 0x2a, 0x06 }, /* -1 */
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{0x00, 0x04, 0x07, 0x20, 0x20, 0x20, 0x06 }, /* 0 */
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{0x00, 0x04, 0x07, 0x20, 0x24, 0x16, 0x06 }, /* +1 */
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{0x00, 0x04, 0x07, 0x20, 0x28, 0x0c, 0x06 }, /* +2 */
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};
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#define NUM_SATURATION_LEVELS (5)
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static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
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{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
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{0x00, 0x02, 0x03, 0x28, 0x28 }, /* -2 */
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{0x00, 0x02, 0x03, 0x38, 0x38 }, /* -1 */
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{0x00, 0x02, 0x03, 0x48, 0x48 }, /* 0 */
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{0x00, 0x02, 0x03, 0x58, 0x58 }, /* +1 */
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{0x00, 0x02, 0x03, 0x58, 0x58 }, /* +2 */
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};
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#if 0
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#define CIF_HSIZE (400)
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#define CIF_VSIZE (296)
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#define SVGA_HSIZE (800)
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#define SVGA_VSIZE (600)
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#define UXGA_HSIZE (1600)
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#define UXGA_VSIZE (1200)
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static const uint8_t default_regs[][2] = {
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{ BANK_SEL, BANK_SEL_DSP },
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{ 0x2c, 0xff },
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{ 0x2e, 0xdf },
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{ BANK_SEL, BANK_SEL_SENSOR },
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{ 0x3c, 0x32 },
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{ CLKRC, 0x80 }, /* Set PCLK divider */
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{ COM2, COM2_OUT_DRIVE_3x }, /* Output drive x2 */
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#ifdef OPENMV2
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{ REG04, 0xF8}, /* Mirror/VFLIP/AEC[1:0] */
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#else
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{ REG04, REG04_SET(REG04_HREF_EN)},
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#endif
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{ COM8, COM8_SET(COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN) },
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{ COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
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{COM10, 0}, //Invert VSYNC
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{ 0x2c, 0x0c },
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{ 0x33, 0x78 },
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{ 0x3a, 0x33 },
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{ 0x3b, 0xfb },
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{ 0x3e, 0x00 },
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{ 0x43, 0x11 },
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{ 0x16, 0x10 },
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{ 0x39, 0x02 },
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{ 0x35, 0x88 },
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{ 0x22, 0x0a },
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{ 0x37, 0x40 },
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{ 0x23, 0x00 },
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{ ARCOM2, 0xa0 },
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{ 0x06, 0x02 },
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{ 0x06, 0x88 },
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{ 0x07, 0xc0 },
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{ 0x0d, 0xb7 },
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{ 0x0e, 0x01 },
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{ 0x4c, 0x00 },
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{ 0x4a, 0x81 },
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{ 0x21, 0x99 },
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{ AEW, 0x40 },
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{ AEB, 0x38 },
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/* AGC/AEC fast mode operating region */
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{ VV, VV_AGC_TH_SET(0x08, 0x02) },
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{ COM19, 0x00 }, /* Zoom control 2 MSBs */
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{ ZOOMS, 0x00 }, /* Zoom control 8 MSBs */
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{ 0x5c, 0x00 },
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{ 0x63, 0x00 },
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{ FLL, 0x00 },
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{ FLH, 0x00 },
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/* Set banding filter */
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{ COM3, COM3_BAND_SET(COM3_BAND_AUTO) },
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{ REG5D, 0x55 },
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{ REG5E, 0x7d },
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{ REG5F, 0x7d },
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{ REG60, 0x55 },
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{ HISTO_LOW, 0x70 },
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{ HISTO_HIGH, 0x80 },
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{ 0x7c, 0x05 },
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{ 0x20, 0x80 },
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{ 0x28, 0x30 },
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{ 0x6c, 0x00 },
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{ 0x6d, 0x80 },
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{ 0x6e, 0x00 },
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{ 0x70, 0x02 },
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|
{ 0x71, 0x94 },
|
|
{ 0x73, 0xc1 },
|
|
{ 0x3d, 0x34 },
|
|
//{ COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
|
|
{ 0x5a, 0x57 },
|
|
{ BD50, 0xbb },
|
|
{ BD60, 0x9c },
|
|
|
|
{ BANK_SEL, BANK_SEL_DSP },
|
|
{ 0xe5, 0x7f },
|
|
{ MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
|
|
{ 0x41, 0x24 },
|
|
{ RESET, RESET_JPEG | RESET_DVP },
|
|
{ 0x76, 0xff },
|
|
{ 0x33, 0xa0 },
|
|
{ 0x42, 0x20 },
|
|
{ 0x43, 0x18 },
|
|
{ 0x4c, 0x00 },
|
|
{ CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
|
|
{ 0x88, 0x3f },
|
|
{ 0xd7, 0x03 },
|
|
{ 0xd9, 0x10 },
|
|
{ R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
|
|
{ 0xc8, 0x08 },
|
|
{ 0xc9, 0x80 },
|
|
{ BPADDR, 0x00 },
|
|
{ BPDATA, 0x00 },
|
|
{ BPADDR, 0x03 },
|
|
{ BPDATA, 0x48 },
|
|
{ BPDATA, 0x48 },
|
|
{ BPADDR, 0x08 },
|
|
{ BPDATA, 0x20 },
|
|
{ BPDATA, 0x10 },
|
|
{ BPDATA, 0x0e },
|
|
{ 0x90, 0x00 },
|
|
{ 0x91, 0x0e },
|
|
{ 0x91, 0x1a },
|
|
{ 0x91, 0x31 },
|
|
{ 0x91, 0x5a },
|
|
{ 0x91, 0x69 },
|
|
{ 0x91, 0x75 },
|
|
{ 0x91, 0x7e },
|
|
{ 0x91, 0x88 },
|
|
{ 0x91, 0x8f },
|
|
{ 0x91, 0x96 },
|
|
{ 0x91, 0xa3 },
|
|
{ 0x91, 0xaf },
|
|
{ 0x91, 0xc4 },
|
|
{ 0x91, 0xd7 },
|
|
{ 0x91, 0xe8 },
|
|
{ 0x91, 0x20 },
|
|
{ 0x92, 0x00 },
|
|
{ 0x93, 0x06 },
|
|
{ 0x93, 0xe3 },
|
|
{ 0x93, 0x03 },
|
|
{ 0x93, 0x03 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x02 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x93, 0x00 },
|
|
{ 0x96, 0x00 },
|
|
{ 0x97, 0x08 },
|
|
{ 0x97, 0x19 },
|
|
{ 0x97, 0x02 },
|
|
{ 0x97, 0x0c },
|
|
{ 0x97, 0x24 },
|
|
{ 0x97, 0x30 },
|
|
{ 0x97, 0x28 },
|
|
{ 0x97, 0x26 },
|
|
{ 0x97, 0x02 },
|
|
{ 0x97, 0x98 },
|
|
{ 0x97, 0x80 },
|
|
{ 0x97, 0x00 },
|
|
{ 0x97, 0x00 },
|
|
{ 0xa4, 0x00 },
|
|
{ 0xa8, 0x00 },
|
|
{ 0xc5, 0x11 },
|
|
{ 0xc6, 0x51 },
|
|
{ 0xbf, 0x80 },
|
|
{ 0xc7, 0x10 },
|
|
{ 0xb6, 0x66 },
|
|
{ 0xb8, 0xA5 },
|
|
{ 0xb7, 0x64 },
|
|
{ 0xb9, 0x7C },
|
|
{ 0xb3, 0xaf },
|
|
{ 0xb4, 0x97 },
|
|
{ 0xb5, 0xFF },
|
|
{ 0xb0, 0xC5 },
|
|
{ 0xb1, 0x94 },
|
|
{ 0xb2, 0x0f },
|
|
{ 0xc4, 0x5c },
|
|
{ 0xa6, 0x00 },
|
|
{ 0xa7, 0x20 },
|
|
{ 0xa7, 0xd8 },
|
|
{ 0xa7, 0x1b },
|
|
{ 0xa7, 0x31 },
|
|
{ 0xa7, 0x00 },
|
|
{ 0xa7, 0x18 },
|
|
{ 0xa7, 0x20 },
|
|
{ 0xa7, 0xd8 },
|
|
{ 0xa7, 0x19 },
|
|
{ 0xa7, 0x31 },
|
|
{ 0xa7, 0x00 },
|
|
{ 0xa7, 0x18 },
|
|
{ 0xa7, 0x20 },
|
|
{ 0xa7, 0xd8 },
|
|
{ 0xa7, 0x19 },
|
|
{ 0xa7, 0x31 },
|
|
{ 0xa7, 0x00 },
|
|
{ 0xa7, 0x18 },
|
|
{ 0x7f, 0x00 },
|
|
{ 0xe5, 0x1f },
|
|
{ 0xe1, 0x77 },
|
|
{ 0xdd, 0x7f },
|
|
{ CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
|
|
{ 0x00, 0x00 }
|
|
};
|
|
|
|
#define CIF_FIX
|
|
|
|
#ifdef CIF_FIX
|
|
static const uint8_t cif_regs[][2] = {
|
|
{BANK_SEL, BANK_SEL_SENSOR},
|
|
{COM7, COM7_RES_CIF},
|
|
{COM1, 0x0A},
|
|
{HSTART, 0x11},
|
|
{HSTOP, 0x43},
|
|
{VSTART, 0x00},
|
|
{VSTOP, 0x25},
|
|
{REG32, 0x89},
|
|
{BD50, 0xca},
|
|
{BD60, 0xa8},
|
|
{0x5a, 0x23},
|
|
{0x6d, 0x00},
|
|
{0x3d, 0x38},
|
|
{0x39, 0x92},
|
|
{0x35, 0xda},
|
|
{0x22, 0x1a},
|
|
{0x37, 0xc3},
|
|
{0x23, 0x00},
|
|
{ARCOM2, 0xc0},
|
|
{0x36, 0x1a},
|
|
{0x06, 0x88},
|
|
{0x07, 0xc0},
|
|
{COM4, 0x87},
|
|
{0x0e, 0x41},
|
|
{0x4c, 0x00},
|
|
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
//{R_BYPASS, R_BYPASS_DSP_BYPAS},
|
|
{RESET, RESET_DVP},
|
|
|
|
{HSIZE8,(CIF_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
|
|
{VSIZE8,(CIF_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
|
|
{SIZEL, ((CIF_HSIZE>>6)&0x40) | ((CIF_HSIZE&0x7)<<3) | (CIF_VSIZE&0x7)},/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
|
|
{HSIZE, ((CIF_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0]= HSIZE/4 */
|
|
{VSIZE, ((CIF_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0]= VSIZE/4 */
|
|
{XOFFL, 0x00 }, /* OFFSET_X[7:0] */
|
|
{YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
|
|
{VHYX, ((CIF_VSIZE>>3)&0x80) | ((CIF_HSIZE>>7)&0x08) }, /* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
|
|
{TEST, (CIF_HSIZE>>4)&0x80}, /* H_SIZE[9] */
|
|
|
|
{CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN},
|
|
{CTRLI, CTRLI_LP_DP | 0x00},/* H_DIVIDER[2:0]/V_DIVIDER[2:0] */
|
|
|
|
{R_DVP_SP, R_DVP_SP_AUTO_MODE},
|
|
//{R_BYPASS, R_BYPASS_DSP_EN},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
#endif
|
|
|
|
static const uint8_t svga_regs[][2] = {
|
|
{ BANK_SEL, BANK_SEL_SENSOR },
|
|
{ COM7, COM7_RES_SVGA},/* DSP input image resoultion and window size control */
|
|
{ COM1, 0x0A }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
|
|
{ REG32, REG32_SVGA },
|
|
|
|
{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIF=0x11 */
|
|
{ HSTOP, 0x43 }, /* UXGA=0x75, SVGA/CIF=0x43 */
|
|
|
|
{ VSTART, 0x00 }, /* UXGA=0x01, SVGA/CIF=0x00 */
|
|
{ VSTOP, 0x4b }, /* UXGA=0x97, SVGA/CIF=0x4b */
|
|
{ 0x3d, 0x38 }, /* UXGA=0x34, SVGA/CIF=0x38 */
|
|
|
|
{ 0x35, 0xda },//88
|
|
{ 0x22, 0x1a },//0a
|
|
{ 0x37, 0xc3 },//40
|
|
{ 0x34, 0xc0 },//a0
|
|
{ 0x06, 0x88 },//02
|
|
{ COM4, 0x87 },//b7
|
|
{ 0x0e, 0x41 },//01
|
|
{ 0x42, 0x03 },//83
|
|
|
|
/* Set DSP input image size and offset.
|
|
The sensor output image can be scaled with OUTW/OUTH */
|
|
{ BANK_SEL, BANK_SEL_DSP },
|
|
{ R_BYPASS, R_BYPASS_DSP_BYPAS },
|
|
{ RESET, RESET_DVP },
|
|
|
|
{ HSIZE8, (SVGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
|
|
{ VSIZE8, (SVGA_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
|
|
{ SIZEL, ((SVGA_HSIZE>>6)&0x40) | ((SVGA_HSIZE&0x7)<<3) | (SVGA_VSIZE&0x7)},/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
|
|
{ HSIZE, ((SVGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0]= HSIZE/4 */
|
|
{ VSIZE, ((SVGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0]= VSIZE/4 */
|
|
{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
|
|
{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
|
|
{ VHYX, ((SVGA_VSIZE>>3)&0x80) | ((SVGA_HSIZE>>7)&0x08) }, /* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
|
|
{ TEST, (SVGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
|
|
|
|
{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN | CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
|
|
{ CTRLI, CTRLI_LP_DP | 0x00},/* H_DIVIDER[2:0]/V_DIVIDER[2:0] */
|
|
|
|
{ R_DVP_SP, R_DVP_SP_AUTO_MODE},/* DVP prescalar */
|
|
{ R_BYPASS, R_BYPASS_DSP_EN },
|
|
{ RESET, 0x00 },
|
|
{0, 0},
|
|
};
|
|
|
|
static const uint8_t uxga_regs[][2] = {
|
|
{ BANK_SEL, BANK_SEL_SENSOR },
|
|
/* DSP input image resoultion and window size control */
|
|
{ COM7, COM7_RES_UXGA},
|
|
{ COM1, 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
|
|
{ REG32, REG32_UXGA }, /* UXGA=0x36, SVGA/CIF=0x09 */
|
|
|
|
{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIF=0x11 */
|
|
{ HSTOP, 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
|
|
|
|
{ VSTART, 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
|
|
{ VSTOP, 0x97 }, /* UXGA=0x97, SVGA/CIF=0x4b */
|
|
{ 0x3d, 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
|
|
|
|
{ 0x35, 0x88 },
|
|
{ 0x22, 0x0a },
|
|
{ 0x37, 0x40 },
|
|
{ 0x34, 0xa0 },
|
|
{ 0x06, 0x02 },
|
|
{ 0x0d, 0xb7 },
|
|
{ 0x0e, 0x01 },
|
|
{ 0x42, 0x83 },
|
|
|
|
/* Set DSP input image size and offset.
|
|
The sensor output image can be scaled with OUTW/OUTH */
|
|
{ BANK_SEL, BANK_SEL_DSP },
|
|
{ R_BYPASS, R_BYPASS_DSP_BYPAS },
|
|
|
|
{ RESET, RESET_DVP },
|
|
{ HSIZE8, (UXGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
|
|
{ VSIZE8, (UXGA_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
|
|
|
|
/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
|
|
{ SIZEL, ((UXGA_HSIZE>>6)&0x40) | ((UXGA_HSIZE&0x7)<<3) | (UXGA_VSIZE&0x7)},
|
|
|
|
{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
|
|
{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
|
|
{ HSIZE, ((UXGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
|
|
{ VSIZE, ((UXGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
|
|
|
|
/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
|
|
{ VHYX, ((UXGA_VSIZE>>3)&0x80) | ((UXGA_HSIZE>>7)&0x08) },
|
|
{ TEST, (UXGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
|
|
|
|
{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
|
|
CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
|
|
|
|
/* H_DIVIDER/V_DIVIDER */
|
|
{ CTRLI, CTRLI_LP_DP | 0x00},
|
|
/* DVP prescalar */
|
|
{ R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x04},
|
|
|
|
{ R_BYPASS, R_BYPASS_DSP_EN },
|
|
{ RESET, 0x00 },
|
|
{0, 0},
|
|
};
|
|
|
|
static const uint8_t jpeg_regs[][2] = {
|
|
{ BANK_SEL, BANK_SEL_DSP },
|
|
{ RESET, RESET_DVP},
|
|
{ IMAGE_MODE, IMAGE_MODE_JPEG_EN|IMAGE_MODE_RGB565 },
|
|
{ 0xD7, 0x03 },
|
|
{ 0xE1, 0x77 },
|
|
{ QS, 0x0C },
|
|
{ RESET, 0x00 },
|
|
{0, 0},
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_cif_qcif[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0x32},
|
|
{VSIZE8, 0x25},
|
|
{SIZEL, 0x00},
|
|
{HSIZE, 0x64},
|
|
{VSIZE, 0x4a},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x00},
|
|
{TEST, 0x00},
|
|
{CTRL2, 0x3d},
|
|
{CTRLI, 0x89},
|
|
{ZMOW, 0x2c},
|
|
{ZMOH, 0x24},
|
|
{ZMHH, 0x00},
|
|
{R_DVP_SP, 0x04},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_cif_qvga[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0x32},
|
|
{VSIZE8, 0x25},
|
|
{SIZEL, 0x00},
|
|
{CTRL2, 0x3d},
|
|
{CTRLI, 0x00},
|
|
{HSIZE, 0x64},
|
|
{VSIZE, 0x4a},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x00},
|
|
{TEST, 0x00},
|
|
{ZMOW, 0x50},
|
|
{ZMOH, 0x3c},
|
|
{ZMHH, 0x00},
|
|
{R_DVP_SP, 0x04},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
// 14.28fps@24MHz
|
|
const DRAM_ATTR uint8_t ov2640_settings_svga[][2] = {
|
|
{BANK_SEL, BANK_SEL_SENSOR},
|
|
{COM7, COM7_SRST},
|
|
//delay 1ms
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{0x2c, 0xff},
|
|
{0x2e, 0xdf},
|
|
{BANK_SEL, BANK_SEL_SENSOR},
|
|
{0x3c, 0x32},
|
|
{0x11, 0x01},
|
|
{0x09, 0x02},
|
|
{0x04, 0x38},
|
|
{0x13, 0xe5},
|
|
{0x14, 0x48},
|
|
{0x2c, 0x0c},
|
|
{0x33, 0x78},
|
|
{0x3a, 0x33},
|
|
{0x3b, 0xfB},
|
|
{0x3e, 0x00},
|
|
{0x43, 0x11},
|
|
{0x16, 0x10},
|
|
{0x39, 0x92},
|
|
{0x35, 0xda},
|
|
{0x22, 0x1a},
|
|
{0x37, 0xc3},
|
|
{0x23, 0x00},
|
|
{0x34, 0xc0},
|
|
{0x36, 0x1a},
|
|
{0x06, 0x88},
|
|
{0x07, 0xc0},
|
|
{0x0d, 0x87},
|
|
{0x0e, 0x41},
|
|
{0x4c, 0x00},
|
|
{0x4a, 0x81},
|
|
{0x21, 0x99},
|
|
{0x24, 0x40},
|
|
{0x25, 0x38},
|
|
{0x26, 0x82},
|
|
{0x5c, 0x00},
|
|
{0x63, 0x00},
|
|
{0x46, 0x22},
|
|
{0x61, 0x70},
|
|
{0x62, 0x80},
|
|
{0x7c, 0x05},
|
|
{0x20, 0x80},
|
|
{0x28, 0x30},
|
|
{0x6c, 0x00},
|
|
{0x6d, 0x80},
|
|
{0x6e, 0x00},
|
|
{0x70, 0x02},
|
|
{0x71, 0x94},
|
|
{0x73, 0xc1},
|
|
{0x3d, 0x34},
|
|
{0x5a, 0x23},
|
|
{0x4f, 0xbb},
|
|
{0x50, 0x9c},
|
|
{0x12, 0x40},
|
|
{0x17, 0x11},
|
|
{0x18, 0x43},
|
|
{0x19, 0x00},
|
|
{0x1a, 0x4b},
|
|
{0x32, 0x09},
|
|
{0x37, 0xc0},
|
|
{0x4f, 0xca},
|
|
{0x50, 0xa8},
|
|
{0x6d, 0x00},
|
|
{0x3d, 0x38},
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{0xe5, 0x7f},
|
|
{0xf9, 0xc0},
|
|
{0x41, 0x24},
|
|
{0xe0, 0x14},
|
|
{0x76, 0xff},
|
|
{0x33, 0xa0},
|
|
{0x42, 0x20},
|
|
{0x43, 0x18},
|
|
{0x4c, 0x00},
|
|
{0x87, 0xd0},
|
|
{0x88, 0x3f},
|
|
{0xd7, 0x03},
|
|
{0xd9, 0x10},
|
|
{0xd3, 0x82},
|
|
{0xc8, 0x08},
|
|
{0xc9, 0x80},
|
|
{0x7c, 0x00},
|
|
{0x7d, 0x00},
|
|
{0x7c, 0x03},
|
|
{0x7d, 0x48},
|
|
{0x7d, 0x48},
|
|
{0x7c, 0x08},
|
|
{0x7d, 0x20},
|
|
{0x7d, 0x10},
|
|
{0x7d, 0x0e},
|
|
{0x90, 0x00},
|
|
{0x91, 0x0e},
|
|
{0x91, 0x1a},
|
|
{0x91, 0x31},
|
|
{0x91, 0x5a},
|
|
{0x91, 0x69},
|
|
{0x91, 0x75},
|
|
{0x91, 0x7e},
|
|
{0x91, 0x88},
|
|
{0x91, 0x8f},
|
|
{0x91, 0x96},
|
|
{0x91, 0xa3},
|
|
{0x91, 0xaf},
|
|
{0x91, 0xc4},
|
|
{0x91, 0xd7},
|
|
{0x91, 0xe8},
|
|
{0x91, 0x20},
|
|
{0x92, 0x00},
|
|
{0x93, 0x06},
|
|
{0x93, 0xe3},
|
|
{0x93, 0x05},
|
|
{0x93, 0x05},
|
|
{0x93, 0x00},
|
|
{0x93, 0x04},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x96, 0x00},
|
|
{0x97, 0x08},
|
|
{0x97, 0x19},
|
|
{0x97, 0x02},
|
|
{0x97, 0x0c},
|
|
{0x97, 0x24},
|
|
{0x97, 0x30},
|
|
{0x97, 0x28},
|
|
{0x97, 0x26},
|
|
{0x97, 0x02},
|
|
{0x97, 0x98},
|
|
{0x97, 0x80},
|
|
{0x97, 0x00},
|
|
{0x97, 0x00},
|
|
{0xc3, 0xed},
|
|
{0xa4, 0x00},
|
|
{0xa8, 0x00},
|
|
{0xc5, 0x11},
|
|
{0xc6, 0x51},
|
|
{0xbf, 0x80},
|
|
{0xc7, 0x10},
|
|
{0xb6, 0x66},
|
|
{0xb8, 0xA5},
|
|
{0xb7, 0x64},
|
|
{0xb9, 0x7C},
|
|
{0xb3, 0xaf},
|
|
{0xb4, 0x97},
|
|
{0xb5, 0xFF},
|
|
{0xb0, 0xC5},
|
|
{0xb1, 0x94},
|
|
{0xb2, 0x0f},
|
|
{0xc4, 0x5c},
|
|
{0xc0, 0x64},
|
|
{0xc1, 0x4B},
|
|
{0x8c, 0x00},
|
|
{0x86, 0x3D},
|
|
{0x50, 0x00},
|
|
{0x51, 0xC8},
|
|
{0x52, 0x96},
|
|
{0x53, 0x00},
|
|
{0x54, 0x00},
|
|
{0x55, 0x00},
|
|
{0x5a, 0xC8},
|
|
{0x5b, 0x96},
|
|
{0x5c, 0x00},
|
|
{0xd3, 0x82},
|
|
{0xc3, 0xed},
|
|
{0x7f, 0x00},
|
|
{0xda, 0x00},
|
|
{0xe5, 0x1f},
|
|
{0xe1, 0x67},
|
|
{RESET, 0x00},
|
|
{0xdd, 0x7f},
|
|
{R_BYPASS, R_BYPASS_DSP_EN},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_svga_qcif[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0x64},
|
|
{VSIZE8, 0x4B},
|
|
{SIZEL, 0x00},
|
|
{CTRL2, 0x3D},
|
|
{CTRLI, 0x92},
|
|
{HSIZE, 0xC8},
|
|
{VSIZE, 0x96},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x00},
|
|
{ZMOW, 0x2C},
|
|
{ZMOH, 0x24},
|
|
{ZMHH, 0x00},
|
|
{R_DVP_SP, 0x04},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_svga_qvga[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0x64},
|
|
{VSIZE8, 0x4B},
|
|
{SIZEL, 0x00},
|
|
{CTRL2, 0x3D},
|
|
{CTRLI, 0x89},
|
|
{HSIZE, 0xC8},
|
|
{VSIZE, 0x96},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x00},
|
|
{ZMOW, 0x50},
|
|
{ZMOH, 0x3c},
|
|
{ZMHH, 0x00},
|
|
{R_DVP_SP, 0x04},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_svga_cif[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0x64},
|
|
{VSIZE8, 0x4B},
|
|
{SIZEL, 0x00},
|
|
{CTRL2, 0x3D},
|
|
{CTRLI, 0x89},
|
|
{HSIZE, 0xC8},
|
|
{VSIZE, 0x96},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x00},
|
|
{ZMOW, 0x58},
|
|
{ZMOH, 0x48},
|
|
{ZMHH, 0x00},
|
|
{R_DVP_SP, 0x04},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_svga_vga[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0x64},
|
|
{VSIZE8, 0x4B},
|
|
{SIZEL, 0x00},
|
|
{CTRL2, 0x3D},
|
|
{CTRLI, 0x00},
|
|
{HSIZE, 0xC8},
|
|
{VSIZE, 0x96},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x00},
|
|
{ZMOW, 0xA0},
|
|
{ZMOH, 0x78},
|
|
{ZMHH, 0x00},
|
|
{R_DVP_SP, 0x82},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
// 14.28fps@24MHz?
|
|
const DRAM_ATTR uint8_t ov2640_settings_uxga[][2] = {
|
|
{BANK_SEL, BANK_SEL_SENSOR},
|
|
{COM7, COM7_SRST},
|
|
//delay 1ms
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{0x2c, 0xff},
|
|
{0x2e, 0xdf},
|
|
{BANK_SEL, BANK_SEL_SENSOR},
|
|
{0x3c, 0x32},
|
|
{0x11, 0x00},
|
|
{0x09, 0x02},
|
|
{0x04, 0x28},
|
|
{0x13, 0xe5},
|
|
{0x14, 0x48},
|
|
{0x2c, 0x0c},
|
|
{0x33, 0x78},
|
|
{0x3a, 0x33},
|
|
{0x3b, 0xfB},
|
|
{0x3e, 0x00},
|
|
{0x43, 0x11},
|
|
{0x16, 0x10},
|
|
{0x39, 0x82},
|
|
{0x35, 0x88},
|
|
{0x22, 0x0a},
|
|
{0x37, 0x40},
|
|
{0x23, 0x00},
|
|
{0x34, 0xa0},
|
|
//{0x36, 0x1a},
|
|
{0x06, 0x02},
|
|
{0x07, 0xc0},
|
|
{0x0d, 0xb7},
|
|
{0x0e, 0x01},
|
|
{0x4c, 0x00},
|
|
{0x4a, 0x81},
|
|
{0x21, 0x99},
|
|
{0x24, 0x40},
|
|
{0x25, 0x38},
|
|
{0x26, 0x82},
|
|
{0x5c, 0x00},
|
|
{0x63, 0x00},
|
|
{0x46, 0x3f},
|
|
{0x0c, 0x3c},
|
|
{0x61, 0x70},
|
|
{0x62, 0x80},
|
|
{0x7c, 0x05},
|
|
{0x20, 0x80},
|
|
{0x28, 0x30},
|
|
{0x6c, 0x00},
|
|
{0x6d, 0x80},
|
|
{0x6e, 0x00},
|
|
{0x70, 0x02},
|
|
{0x71, 0x94},
|
|
{0x73, 0xc1},
|
|
{0x3d, 0x34},
|
|
{0x5a, 0x57},
|
|
{0x4f, 0xbb},
|
|
{0x50, 0x9c},
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{0xe5, 0x7f},
|
|
{0xf9, 0xc0},
|
|
{0x41, 0x24},
|
|
{0xe0, 0x14},
|
|
{0x76, 0xff},
|
|
{0x33, 0xa0},
|
|
{0x42, 0x20},
|
|
{0x43, 0x18},
|
|
{0x4c, 0x00},
|
|
{0x87, 0xd0},
|
|
{0x88, 0x3f},
|
|
{0xd7, 0x03},
|
|
{0xd9, 0x10},
|
|
{0xd3, 0x82},
|
|
{0xc8, 0x08},
|
|
{0xc9, 0x80},
|
|
{0x7c, 0x00},
|
|
{0x7d, 0x00},
|
|
{0x7c, 0x03},
|
|
{0x7d, 0x48},
|
|
{0x7d, 0x48},
|
|
{0x7c, 0x08},
|
|
{0x7d, 0x20},
|
|
{0x7d, 0x10},
|
|
{0x7d, 0x0e},
|
|
{0x90, 0x00},
|
|
{0x91, 0x0e},
|
|
{0x91, 0x1a},
|
|
{0x91, 0x31},
|
|
{0x91, 0x5a},
|
|
{0x91, 0x69},
|
|
{0x91, 0x75},
|
|
{0x91, 0x7e},
|
|
{0x91, 0x88},
|
|
{0x91, 0x8f},
|
|
{0x91, 0x96},
|
|
{0x91, 0xa3},
|
|
{0x91, 0xaf},
|
|
{0x91, 0xc4},
|
|
{0x91, 0xd7},
|
|
{0x91, 0xe8},
|
|
{0x91, 0x20},
|
|
{0x92, 0x00},
|
|
{0x93, 0x06},
|
|
{0x93, 0xe3},
|
|
{0x93, 0x05},
|
|
{0x93, 0x05},
|
|
{0x93, 0x00},
|
|
{0x93, 0x04},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x93, 0x00},
|
|
{0x96, 0x00},
|
|
{0x97, 0x08},
|
|
{0x97, 0x19},
|
|
{0x97, 0x02},
|
|
{0x97, 0x0c},
|
|
{0x97, 0x24},
|
|
{0x97, 0x30},
|
|
{0x97, 0x28},
|
|
{0x97, 0x26},
|
|
{0x97, 0x02},
|
|
{0x97, 0x98},
|
|
{0x97, 0x80},
|
|
{0x97, 0x00},
|
|
{0x97, 0x00},
|
|
{0xc3, 0xed},
|
|
{0xa4, 0x00},
|
|
{0xa8, 0x00},
|
|
{0xc5, 0x11},
|
|
{0xc6, 0x51},
|
|
{0xbf, 0x80},
|
|
{0xc7, 0x10},
|
|
{0xb6, 0x66},
|
|
{0xb8, 0xA5},
|
|
{0xb7, 0x64},
|
|
{0xb9, 0x7C},
|
|
{0xb3, 0xaf},
|
|
{0xb4, 0x97},
|
|
{0xb5, 0xFF},
|
|
{0xb0, 0xC5},
|
|
{0xb1, 0x94},
|
|
{0xb2, 0x0f},
|
|
{0xc4, 0x5c},
|
|
{0xc0, 0xc8},
|
|
{0xc1, 0x96},
|
|
{0x86, 0x3d},
|
|
{0x50, 0x00},
|
|
{0x51, 0x90},
|
|
{0x52, 0x2c},
|
|
{0x53, 0x00},
|
|
{0x54, 0x00},
|
|
{0x55, 0x88},
|
|
{0x57, 0x00},
|
|
{0x5a, 0x90},
|
|
{0x5b, 0x2c},
|
|
{0x5c, 0x05},
|
|
{0xc3, 0xed},
|
|
{0x7f, 0x00},
|
|
{0xda, 0x00},
|
|
{0xe5, 0x1f},
|
|
{0xe1, 0x67},
|
|
{RESET, 0x00},
|
|
{0xdd, 0x7f},
|
|
{R_BYPASS, R_BYPASS_DSP_EN},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_uxga_xga[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0xC8},
|
|
{VSIZE8, 0x96},
|
|
{SIZEL, 0x00},
|
|
{CTRL2, 0x3D},
|
|
{CTRLI, 0x00},
|
|
{HSIZE, 0x90},
|
|
{VSIZE, 0x2C},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x88},
|
|
{ZMOW, 0x00},
|
|
{ZMOH, 0xC0},
|
|
{ZMHH, 0x01},
|
|
{R_DVP_SP, 0x02},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_uxga_sxga[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_DVP},
|
|
{HSIZE8, 0xc8},
|
|
{VSIZE8, 0x96},
|
|
{CTRL2, 0x3d},
|
|
{CTRLI, 0x00},
|
|
{HSIZE, 0x90},
|
|
{VSIZE, 0x2c},
|
|
{XOFFL, 0x00},
|
|
{YOFFL, 0x00},
|
|
{VHYX, 0x88},
|
|
{TEST, 0x00},
|
|
{ZMOW, 0x40},
|
|
{ZMOH, 0xf0},
|
|
{ZMHH, 0x01},
|
|
{R_DVP_SP, 0x82},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_jpeg1[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_JPEG | RESET_DVP},
|
|
{0xE1, 0x77},
|
|
{0xE5, 0x1F},
|
|
{0xD7, 0x03},
|
|
{0xd9, 0x10},
|
|
{IMAGE_MODE, IMAGE_MODE_JPEG_EN | IMAGE_MODE_HREF_VSYNC},
|
|
{0xdf, 0x00},
|
|
{0x33, 0xa0},
|
|
{0x3c, 0x10},
|
|
{0xd1, 0x07},
|
|
{0xd2, 0x02},
|
|
{0xd2, 0x00},
|
|
{R_DVP_SP, 0x04},
|
|
{0xeb, 0x30},
|
|
{0xdd, 0x7f},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
|
|
const DRAM_ATTR uint8_t ov2640_settings_jpeg2[][2] = {
|
|
{BANK_SEL, BANK_SEL_DSP},
|
|
{RESET, RESET_JPEG | RESET_DVP},
|
|
{0xE1, 0x77},
|
|
{0xE5, 0x1F},
|
|
{0xD7, 0x03},
|
|
{IMAGE_MODE, IMAGE_MODE_JPEG_EN},
|
|
{0xD9, 0x10},
|
|
{0x33, 0x80},
|
|
{0x3c, 0x10},
|
|
{R_DVP_SP, 0x04},
|
|
{0xeb, 0x30},
|
|
{0xdd, 0x7f},
|
|
{RESET, 0x00},
|
|
{0, 0}
|
|
};
|
|
#endif
|
|
|
|
#endif /* _OV2640_SETTINGS_H_ */
|